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1.2.6 Reset Operations
LHF00L28
t PHQV
22
RST#
(P)
V IH
V IL
t PLPH
DQ 15-0 (D/Q) OH
V
V OL
High Z
(A) Reset during Read Array Mode
ABORT
SR.7="1"
VALID
OUTPUT
t PLRH
COMPLETE
t PHQV
RST#
(P)
V IH
V IL
t PLPH
DQ 15-0 (D/Q) OH
DQ 15-0 (D/Q) OH
V CC
RST#
V
V OL
V CC (min)
GND
V IH
(P)
V IL
V
V OL
High Z
High Z
(B) Reset during Erase or Program Mode
t 2VPH
(C) RST# rising timing
t VHQV
t PHQV
VALID
OUTPUT
VALID
OUTPUT
Figure 8. AC Waveform for Reset Operations
Reset AC Specifications (V CC =2.7V-3.6V, T A =-40 ° C to +85 ° C)
Symbol
Parameter
Notes
Min.
Max.
Unit
t PLPH
t PLRH
t 2VPH
t VHQV
RST# Low to Reset during Read
(RST# should be low during power-up.)
RST# Low to Reset during Erase or Program
V CC 2.7V to RST# High
V CC 2.7V to Output Delay
1, 2, 3
1, 3, 4
1, 3, 5
3
100
100
22
1
ns
μ s
ns
ms
NOTES:
1. A reset time, t PHQV , is required from the later of SR.7 (RY/BY#) going "1" (High Z) or RST# going high until outputs are
valid. Refer to AC Characteristics - Read-Only Operations for t PHQV .
2. t PLPH is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If RST# asserted while a block erase, full chip erase, program or OTP program operation is not executing, the reset will
complete within 100ns.
5. When the device power-up, holding RST# low minimum 100ns is required after V CC has been in predefined range and
also has been in stable there.
Rev. 2.45
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